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PIC16LC67-04I/SO データシートの表示(PDF) - Microchip Technology

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PIC16LC67-04I/SO
Microchip
Microchip Technology 
PIC16LC67-04I/SO Datasheet PDF : 336 Pages
First Prev 271 272 273 274 275 276 277 278 279 280 Next Last
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 23-15: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
RC7/RX/DT
pin
121
121
120
122
Note: Refer to Figure 23-1 for load conditions
TABLE 23-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Parameter Sym
No.
Characteristic
Min Typ† Max Units Conditions
120*
TckH2dtV SYNC XMIT (MASTER & SLAVE) PIC16C66/67
Clock high to data out valid
PIC16LC66/67
80
ns
— 100
ns
121* Tckrf
Clock out rise time and fall time PIC16C66/67
45
ns
(Master Mode)
PIC16LC66/67
50
ns
122* Tdtrf
Data out rise time and fall time PIC16C66/67
45
ns
PIC16LC66/67
50
ns
* These parameters are characterized but not tested.
†: Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 23-16: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
RC7/RX/DT
pin
125
126
Note: Refer to Figure 23-1 for load conditions
TABLE 23-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter Sym
No.
Characteristic
Min
Typ† Max Units Conditions
125*
TdtV2ckL SYNC RCV (MASTER & SLAVE)
Data setup before CK (DT setup time)
15
ns
126*
TckL2dtl Data hold after CK (DT hold time)
15
ns
* These parameters are characterized but not tested.
†: Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30234D-page 280
© 1997 Microchip Technology Inc.

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