PIC16(L)F1512/3
FIGURE 25-8:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Start-Up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
33
32
I/O pins
Note 1: Asserted low.
30
31
34
34
FIGURE 25-9:
VDD
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VBOR
VBOR and VHYST
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
37
Reset
(due to BOR)
33(1)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Words is programmed to ‘0’.
2 ms delay if PWRTE = 0 and VREGEN = 1.
2012-2014 Microchip Technology Inc.
DS40001624C-page 299