ST7MC2N6T3 データシートの表示（PDF） - STMicroelectronics

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ST7MC2N6T3

8-bit MCU with nested interrupts, Flash, 10-bit ADC, brushless motor control, five timers, SPI, LINSCI™

STMicroelectronics 

ST7MC1xx/ST7MC2xx

6 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for

securing the application in critical situations (for

example in case of a power brown-out), and re-

ducing the number of external components. An

overview is shown in Figure 13.

For more details, refer to dedicated parametric

section.

Main features

■ Reset Sequence Manager (RSM)

■ 1 Crystal/Ceramic resonator oscillator

■ System Integrity Management (SI)

– Main supply Low voltage detection (LVD)

– Auxiliary Voltage detector (AVD) with interrupt

capability for monitoring the main supply

– Clock Security System (CSS) with the VCO of

the PLL, providing a backup safe oscillator

– Clock Detector

– PLL which can be used to multiply the fre-

quency by 2 if the clock frequency input is

8MHz

Figure 13. Clock, Reset and Supply Block Diagram

SYSTEM INTEGRITY MANAGEMENT

OSC2

OSC1

fOSC

CLOCK SECURITY SYSTEM

OSCILLATOR

1/2

fOSC

DIV2 OPT

8Mhz PLL

Safeosc

16Mhz

lock

fCLK MAIN CLOCK fCPU

CONTROLLER

WITH REALTIME

CLOCK (MCC/RTC)

fMTC

CKSEL

SICSR, page 1

PA

GE

0

VCO LO PLL

EN CK EN

0

CK

SEL

0

Clock Detector

RESET

RESET SEQUENCE

MANAGER

(RSM)

AVD Interrupt Request

SICSR, page 0

PA AVD AVD LVD

GE IE F RF

0

CSS CSS WDG

IE D RF

WATCHDOG

TIMER (WDG)

VSS

VDD*

CSS Interrupt Request

LOW VOLTAGE

DETECTOR

(LVD)

AUXILIARY VOLTAGE

DETECTOR

(AVD)

* It is recommended to decouple the power supply by placing a 0.1µF capacitor as close as possible to VDD

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