PIC18F010T-I/SN 데이터 시트보기 (PDF) - Microchip Technology

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PIC18F010T-I/SN

High Performance Microcontrollers

Microchip Technology 

PIC18F010/020

REGISTER 12-3: CONFIG2H: CONFIGURATION REGISTER 2H (ADDRESS 300003h)

R/P-1

U-0

reserved

—

bit 7

R/P-1

R/P-1

R/P-1

R/P-1

R/P-1

STVRE WDTLE WDPS2 WDPS1 WDPS0

R/P-1

WDTE

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3-1

bit 0

Reserved

Unimplemented: Read as ’0’

STVRE: Stack Full/Underflow Reset Enable bit

1 = Reset on stack full/underflow enabled

0 = Disabled

WDTLE: Watchdog Timer Long Delay Enable bit

1 = Use WDPS<2:0> bits to set delay

0 = Enable long postscaler divider; 16 x WDPS<2:0> bits

WDPS2:WDPS0: Watchdog Timer Postscale Select bits

111 = 1:128

110 = 1:64

101 = 1:32

100 = 1:16

011 = 1:8

010 = 1:4

001 = 1:2

000 = 1:1

WDTE: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled (control is placed on the SWDTE bit)

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

1 = Bit is set

U = Unimplemented bit, read as ‘0’

0 = Bit is cleared x = Bit is unknown

DS41142A-page 86

Preliminary

 2001 Microchip Technology Inc.

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