PIC18F010T-I/SN 데이터 시트보기 (PDF) - Microchip Technology

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PIC18F010T-I/SN

High Performance Microcontrollers

Microchip Technology 

PIC18F010/020

12.2 Watchdog Timer (WDT)

The Watchdog Timer is a free running, on-chip RC

oscillator, which does not require any external compo-

nents. This RC oscillator is separate from the internal

oscillator of the OSC1/CLKI pin. That means that the

WDT will run, even if the clock on the OSC1/CLKI and

OSC2/CLKO/RA6 pins of the device has been stopped,

for example, by execution of a SLEEP instruction.

During normal operation, a WDT time-out generates a

device RESET (Watchdog Timer Reset). If the device is

in SLEEP mode, a WDT time-out causes the device to

wake-up and continue with normal operation (Watch-

dog Timer Wake-up). The TO bit in the RCON register

will be cleared upon a WDT time-out.

The Watchdog Timer is enabled/disabled by a device

configuration bit. If the WDT is enabled, software exe-

cution may not disable this function. When the WDTEN

configuration bit is cleared, the SWDTEN bit enables/

disables the operation of the WDT.

REGISTER 12-5: WDTCON REGISTER

U-0

U-0

U-0

—

—

—

bit 7

The WDT time-out period values may be found in the

Electrical Specifications section under parameter #31.

Values for the WDT postscaler may be assigned using

the configuration bits or in software.

Note:

The CLRWDT and SLEEP instructions clear

the WDT and the postscaler, if assigned to

the WDT and prevent it from timing out and

generating a device RESET condition.

Note:

When a CLRWDT instruction is executed

and the prescaler is assigned to the WDT,

the prescaler count will be cleared, but the

prescaler assignment is not changed.

12.2.1 CONTROL REGISTER

Register 12-5 shows the WDTCON register. This is a

readable and writable register, which contains a control

bit that allows software to override the WDT enable

configuration bit, only when the configuration bit has

disabled the WDT.

U-0

U-0

U-0

U-0

R/W-0

—

—

—

—

SWDTEN

bit 0

bit 7-1

bit 0

Unimplemented: Read as ’0’

SWDTEN: Software Controlled Watchdog Timer Enable bit

1 = Watchdog Timer is on

0 = Watchdog Timer is turned off

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

1 = Bit is set

U = Unimplemented bit, read as ‘0’

0 = Bit is cleared x = Bit is unknown

Note: This register must be unlocked to modify, see Section 12.4.

DS41142A-page 88

Preliminary

 2001 Microchip Technology Inc.

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