CL-PS7500FE 데이터 시트보기 (PDF) - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

NOTE: Since the upper and lower panels are simultaneously driven, the CL-PS7500FE only produces data for half

the total number of lines on the dual panel. The vertical registers must be programmed as if there were only

one panel.

The CL-PS7500FE requests data in two qword units. The first qword the memory controller delivers is for

the upper half-screen; the second qword is for the lower half-screen. The ARM processor then serializes

the data into two simultaneous bitstreams, as previously described. One-, 2-, or 4-bpp can be selected.

For details of the CL-PS7500FE register programming requirements for duplex DMA, see Chapter 10.

12.5.3 Single-Panel Color LCDs

If neither CONREG[13] nor EREG[13] are set, then the ED[7:0] port can be used to gain access to all of

the physical bits out of the video MUX. This allows many other types of display to be driven.

12.6 External Support

The CL-PS7500FE has an 8-bit output port, ED[7:0], and a synchronous clock, ECLK, that have different

functions in different modes. The port is controlled by EREG[1:0] in the control register, that select the

bytes from the video MUX. Additionally, an CL-PS7500FE register bit (bit 1 of the VIDMUX register — see

Section 10.3.28 on page 91) can cause the data selection for the ED port to be modified according to the

state of the ECLK output. This feature is intended to increase the bandwidth for driving color LCD screens.

When this control bit is set low, the behavior of the ED port is as shown below. The bit is intended to be

used with EREG[13] set low. When the VIDMUX bit is high and EREG[1:0] is set low:

q if ECLK is also low – the Red LUT is output on ED[7:0]

q if ECLK is high – the Green LUT is output on ED[7:0]

EREG[1:0] = 0

The Red LUT is output on ED[7:0].

EREG[1:0] = 1

If EREG[13] = 0, the Green LUT is output on ED[7:0].

If EREG[13] = 1, the grayscaled LCD signals are output. ED[7:4] carries the data for the upper half-

screen from the Green LUT, and ED[3:0] carries the data for the lower half-screen from the Ext LUT.

NOTE: Since the data output actually represents 4 pixels for each half-screen, if EREG[13] = 1, data is output at

one quarter of the ARM processor pixel rate.

When EREG[1:0] = 2

if EREG[14] = 0, the Blue LUT is output on ED[7:0].

If EREG[14] = 1, the multiplexed Blue LUT and HiRes cursor data is output on ED[7:0]. See

Section 12.4. Also ED[7:0] is re-timed and delayed by one extra pixel.

When EREG[1:0] = 3

If EREG[12] = 0, ED[3:0] are driven by the Ext LUT and ED[7:4] are driven by the value of

EREG[7:4]. This is intended as a DC control port in this mode.

If EREG[12] = 1, ED[3:0] are delayed by one pixel, so that they are exported from the CL-PS7500FE

in the same pixel as the corresponding analog data. In this configuration, ED[3:0] bits can be used

for supremacy to overlay pictures on a pixel-by-pixel basis. Because several bits are output, analog

fading and mixing on a pixel basis is also possible.

130

VIDEO FEATURES

ADVANCE DATA BOOK v2.0

June 1997

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