CL-PS7500FE 데이터 시트보기 (PDF) - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

19.3 Coprocessor Register Transfer

31

28 27

24 23 22 21 20 19

16 15

12 11

87

43

0

cond

1110

abc L/S

e Fn

Rd

0001

fgh1

i Fm

FLT{cond}<S|D|E>{P|M|Z} Fn, Rd

FIX{cond}{P|M|Z}

Rd, Fm

<WFS|RFS|WFC|RFC>{cond} Rd

When L/S is:

1

the transfer is to an ARM register

0

the transfer is from an ARM register

abc L/S

0000

0001

0010

0011

0100

0101

011x

1000

1010

1100

1110

Mnemonic

FLT

FIX

WFS

RFS

WFC

RFC

Description

Convert integer to floating point

Convert floating point to integer

Write Floating Point Status register

Read Floating Point Status register

Write Floating Point Control register

Read Floating Point Control register

trap: undefined instruction

trap: undefined instruction

trap: undefined instruction

trap: undefined instruction

trap: undefined instruction

Operation

Fn : = Rd

Rd : = Fm

FPSR : = Rd

Rd : = FPSR

FPCR: = Rd

Rd : = FPCR

Note

1

1

NOTES:

1) Supervisor-only instructions.

Definition of the efgh Bits

The definition of the efgh bits is instruction-dependent:

FLT

ef

destination size (Section 19.2)

gh

rounding mode (Section 19.2)

FIX

ef

these bits are reserved and should be zero.

gh

rounding mode (Section 19.2)

178

FLOATING-POINT INSTRUCTION SET

ADVANCE DATA BOOK v2.0

June 1997

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