CL-PS7500FE 데이터 시트보기 (PDF) - Cirrus Logic

부품명

상세내역

제조사

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

Returning from a SWI

To return from a SWI, use MOVS PC, R14_svc. This restores the PC and CPSR, and return to the instruc-

tion following the SWI.

7.4.5 Undefined Instruction Trap

When the ARM processor comes across an instruction that it cannot manage, it takes the undefined

instruction trap. This includes all coprocessor instructions, except MCR and MRC operations that access

the internal control coprocessor.

The trap can be used for software emulation of a coprocessor in a system that does not have the copro-

cessor hardware, or for general-purpose instruction set extension by software emulation.

When the ARM processor takes the undefined instruction trap, it performs the following:

1) Saves the address of the Undefined or coprocessor instruction plus 4 in R14_und; saves CPSR in

SPSR_und.

2) Forces M[4:0]=11011 (Undefined mode) and sets the I bit in the CPSR.

3) Forces the PC to fetch the next instruction from address 0x04.

Returning from an Undefined Instruction Trap

To return from this trap after emulating the failed instruction, use MOVS PC,R14_und. This restores the

CPSR and returns to the instruction following the undefined instruction.

7.4.6 Vector Summary

These are byte addresses and normally contain a branch instruction pointing to the relevant routine.

The FIQ routine might reside at 0x1C onwards, thereby avoiding the need for (and execution time of) a

branch instruction.

Table 7-2. Vector Summary

Address

0x00000000

0x00000004

0x00000008

0x0000000C

0x00000010

0x00000014

0x00000018

0x0000001C

Exception

Reset

Undefined instruction

Software interrupt

Abort (prefetch)

Abort (data)

Reserved

IRQ

FIQ

Mode on Entry

Supervisor

Undefined

Supervisor

Abort

Abort

–

IRQ

FIQ

60

REGISTER DESCRIPTIONS

ADVANCE DATA BOOK v2.0

June 1997

Share Link: