CL-PS7500FE 데이터 시트보기 (PDF) - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

Read

Reset

bit[6]

0

32-bit

1

16-bit

bit[5]

0

half speed mode

1

normal speed

return above values

set to 0x40, that is, 16-bit, slowest access time, and writes disabled.

The output and write enable signals are output on the pins nIOR and nIOW respectively. This reuse of I/O

signals is not expected to cause any difficulties since I/O chip selects is not active during accesses to

ROM space.

9.2 DRAM Interface

The DRAM interface can directly drive four banks of DRAM to give a maximum of 64 Mbytes in each

DRAM bank:

q Four nRAS strobes to select the bank

q Four nCAS strobes to select the byte within the word

q Twelve multiplexed row/column address lines RA[11:0]

The nRAS strobes are decoded directly from bits 27 and 26 of the address. This means that the DRAM

address space is non-contiguous if the entire 64 Mbytes is not used for each bank.

The DRAM controller supports page mode burst cycles with up to 255 sequential accesses in a burst.

Each of the four banks can be a 16- or 32-bit-wide device.

The interface can be programmed to support either Fast Page or EDO type DRAMs. When EDO DRAM

has been selected, the data is latched into CL-PS7500FE one cycle later, taking advantage of the data

latches resident in the output stage of the DRAM. The memory clock frequency can then be increased to

realize the greater sequential access bandwidth available with EDO DRAMs.

NOTE: With a lower frequency memory clock, the interface may support EDO DRAM even without the configuration

bit being set.

Support is provided for CAS-before-RAS refresh, and direct programmability of the nRAS and nCAS out-

puts through a special register allows software to directly control self-refresh DRAM.

DRAM cycle speed is controlled by the frequency of MEMCLK. Non-sequential DRAM cycles require

between five and nine MEMCLK cycles, depending on the selected mode and RAS pre-charge require-

ments. Page mode sequential cycles require two MEMCLK cycles.

9.2.1 DRAM Control Registers

There are three registers associated with DRAM control:

DRAMCR has seven bits, including four (one for each bank) to allow selection between 16- and 32-bit

modes of operation for each bank. Of the three remaining bits:

q One selects EDO memory support

q One inserts an extra wait state between falling nRAS and falling nCAS on read cycles to preserve tRAC

June 1997

ADVANCE DATA BOOK v2.0

69

MEMORY SUBSYSTEMS

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