Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 54. Series 2 Readback Timing Characteristics
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA/B Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA/B Industrial: VDD = 3.0 V to 3.6 V,
–40 °C ≤ TA ≤ +85 °C.
Parameter
Symbol
Min
RD_CFGN to CCLK Setup Time
TS
50
S RD_CFGN High Width to Abort Readback
TRBA
2
CCLK Low Time
TCL
50
E CCLK High Time
TCH
50
CCLK Frequency
FC
—
IC CCLK to RD_DATA Delay
TD
—
V ED RD_CFGN
E U CCLK
D IN RD_DATA
TS
TCH
TCL
TD
BIT 0
BIT 1
TRBA
SELDEICSTCONT Figure 72. Readback Timing Diagram
Max
—
—
—
—
10
50
Unit
ns
CCLK
ns
ns
MHz
ns
BIT 0
5-4536(F)
Lattice Semiconductor
169