ADE3800XT 데이터 시트보기 (PDF) - STMicroelectronics

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ADE3800XT

Analog LCD Display Engine for XGA and SXGA Resolutions with Embedded LVDS and RSDS Transmitters

STMicroelectronics 

Register Description by Block

Register Name

OMUX_CTRL7

OMUX_HALF_LINE_L

OMUX_HALF_LINE_U

OMUX_TEST

Table 33: OMUX Registers (Sheet 3 of 3)

Addr Mode Bits Rst

Description

0C37 R/W

R/W

R/W

R/W

0C38 R/W

0C39 R/W

0C3A R/W

R/W

[7]

00

[6]

[4]

[1]

[0]

[7:0] 00

[3:0] 00

[1]

00

[0]

1: invert RSDS clock 1 (RSDS data pair

12)

0*: normal LVDS PLL clock if LVDS

mode (normal)

1: invert LVDS PLL clock if LVDS mode,

or invert RSDS clock 0 (RSDS data pair

21) if RSDS mode

1: invert LVDS output DE

TCON remapped to PWM

TCON[1] = pwm_a enable

TCON[0] = pwm_b enable

RSDS split buffer half line address =

out_hpixel/2.

out_hpixel has to be multiples of 4.

E.g. for SXGA panel (1280) the value is

640

1: enable RSDS debug mode

1: enable LVDS debug mode

Table 34: OMUX_CTRL Output Modes

OUTPUT MODE OMUX_CTRL1 [0] OMUX_CTRL3 [0]

idle

0

0

LVDS mode

1

0

RVDS mode

0

1

The omux architecture consists of 2 main blocks as shown in Figure 19.

Figure 19: OMUX Architecture

ADE3800

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