ADE3800XT 데이터 시트보기 (PDF) - STMicroelectronics

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ADE3800XT

Analog LCD Display Engine for XGA and SXGA Resolutions with Embedded LVDS and RSDS Transmitters

STMicroelectronics 

Register Description by Block

ADE3800

4.17.1 Output Data

LVDS

56 bits of LVDS data are arranged as shown in Table 35:

Table 35: LVDS output data

LVDS

Output

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

LVDS Data

[6]

lvds_data_o[6:0] AR0

lvds_data_o[13:7] AG1

lvds_data_o[20:14] AB2

lvds_data_o[27:21] AR6

lvds_data_o[34:28] BR0

lvds_data_o[41:35] BAG1

lvds_data_o[48:42] BB2

lvds_data_o[55:49] BR6

[5]

AR1

AG2

AB3

AR7

BR1

BG2

BB3

BR7

[4]

AR2

AG3

AB4

AG6

BR2

BG3

BB4

BG6

[3]

AR3

AG4

AB5

AG7

BR3

BG4

BB5

BG7

[2]

AR4

AG5

HS

AB6

BR4

BG5

HS

BB6

[1]

AR5

AB0

VS

AB7

BR5

BB0

VS

BB7

[0]

AG0

AB1

DE

AReserved

BG0

BB1

DE

BReserved

MSB-LSB Flip

If omux_ctrl1[6] is equal to 1, data are flipped as follows:

lvds_data_out[27:0] =

{lvds_data_o[6:0],lvds_data_o[13:7],lvds_data_o[20:14],lvds_data_o[27:21]}

lvds_data_out[55:28] =

{lvds_data_o[34:28],lvds_data_o[41:35],lvds_data_o[48:42],lvds_data_o[55:49]}

RSDS 128 pin and 100 pin

In RSDS mode, 24/48 data bits are combined into 12/24 pairs for 1 ppc and 2 ppc modes,

respectively.

The split line buffer is to be run in 2 ppc RSDS mode 128 pin only.

98/138

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