CS4952 데이터 시트보기 (PDF) - Cirrus Logic

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CS4952

NTSC/PAL Digital Video Encoder

Cirrus Logic 

CS4952/53

outputs to schedule the proper external delivery of

digital video into the V [7:0] pins. Figure 7 illus-

trates horizontal timing for CCIR601 input in Mas-

ter Mode. Note that the CS4952/3 expects to

receive the first active pixel data on clock cycle 245

(NTSC) when bit SYNC_DLY=0 in the

CONTROL_2 Register (0x02). When

SYNC_DLY=1, it expects the first active pixel data

on clock cycle 246 (NTSC).

Vertical Timing

The CS4952/3 can be selected through the

CONTROL_0 register (0x00) to operate in four

different timing modes: PAL which is 625 vertical

lines 25 frames per second interlaced, NTSC which

is 525 vertical lines 30 frames per second interlaced

and both PAL and NTSC again but in Progressive

Scan where the display is non-interlaced.

The CS4952/3 conforms to standard digital decom-

pression dimensions and does not process digital

input data for the active analog video half lines as

they are typically in the over/underscan region of

televisions. For NTSC, 240 active lines total per

field are processed and for PAL 288 active lines to-

tal per field. Frame vertical dimensions are 480

lines for NTSC and 576 lines for PAL. Table 1

specifies active line numbers for both NTSC and

PAL. Refer to Figure 8 for HSYNC, VSYNC and

FIELD signal timing.

MODE

NTSC

PAL

NTSC Progressive-Scan

PAL Progressive-Scan

FIELD

1, 3

2, 4

1, 3, 5, 7

2, 4, 6, 8

NA

NA

ACTIVE

LINES

22-261

285-524

23-310

336-623

22-261

23-310

Table 1. Vertical Timing

Horizontal Timing

HSYNC is used to synchronize the horizontal input

to output timing in order to provide proper horizon-

tal alignment. HSYNC defaults to an input pin fol-

lowing RESET but switches to output in Master

Mode (CONTROL_0 [4] = 1). Horizontal timing is

referenced to HSYNC transitioning low. For active

video lines, digital video input is to be applied to

the V [7:0] inputs 244 (NTSC) or 264 (PAL), CLK

periods following HSYNC going low to determine

the horizontal alignment of the active video.

NTSC 27MHz Clock Count 1682 1683 1684 1685 1686 • • • 1716 1 2 3 • • • 128 129 • • • 244 245 246 247 248

PAL 27MHz Clock Count 1702 1703 1704 1705 1706 • • • 1728 1 2 3 • • • 128 129 • • • 264 265 266 267 268

CLK

HSYNC* (output)

CB* (output)

V[7:0] Y

(SYNC_DLY=0)

•••

Cr Y

active pixel

#720

V[7:0] Cb Y

(SYNC_DLY=1)

active pixel

#719

Cr Y

active pixel

#720

horizontal blanking

horizontal blanking

Cb Y Cr Y

active pixel active pixel

#1

#2

Cb Y Cr

active pixel active pixel

#1

#2

Figure 7. CCIR601 Input Master Mode Horizontal Timing

DS223PP2

15

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