CS5368(2005) 데이터 시트보기 (PDF) - Cirrus Logic

부품명

상세내역

제조사

CS5368
(Rev.:2005)

114 dB, 192 kHz, 8-Channel A/D Converter

Cirrus Logic 

SERIAL AUDIO INTERFACE - TDM TIMING

The serial audio port is a 3 pin interface consisting of SCLK, LRCK and SDOUT.

Logic "0" = GND = 0 V; Logic "1" = VLS; CL = 20 pF, timing threshold is 50% of VLS.

CS5368

Sample Rates

SCLK Frequency2

SCLK Period

SCLK Duty Cycle

FS setup

FS hold

FS width

SDOUT setup

SDOUT hold

Notes:

Parameter

Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode1

Symbol

-

-

-

1/(256*54 kHz)

before SCLK rising

after SCLK rising

in SCLK cycles

before SCLK rising

after SCLK rising

tPERIOD

tHIGH1

tSETUP1

tHOLD1

tHIGH2

tSETUP2

tHOLD2

Min

2

54

108

-

72.3

30

20

20

3

10

10

Typ

-

-

-

256*Fs

-

-

-

-

-

-

-

Max Unit

54

kHz

108

kHz

216

kHz

-

Hz

-

ns

70

%

-

ns

-

ns

250

-

-

ns

-

ns

1. TDM Quad-Speed Mode only specified to operate correctly at VLS ≥ 3.14 V.

2. In Master mode, the SCLK/LRCK ratio is fixed at 256. In Slave Mode, the SCLK/RCLK ratio can be set

according to preference. However, chip performance is guaranteed only when using the ratios in Section

4.6.9 Master and Slave Clock Frequencies on page 29.

tPERIOD

tHIGH1

SCLK

FS

SDOUT

data

tSET UP1

tHIGH2

newframe

tSET UP2

data

tHOLD2

Figure 3. TDM Timing

tHOLD1

data

OVERFLOW TIMEOUT

Logic "0" = GND = 0 V; Logic "1" = VLS; CL = 15 pF, timing threshold is 50% of VLS.

Parameter

Symbol Min

Typ

Max

OVFL time-out on overrange condition

Fs = 44.1 kHz

Fs = 192 kHz

-

(217-1)/Fs

-

-

2972

-

-

683

-

Table 1. Overflow Timeout

Unit

ms

ms

ms

DS624A1

19

Share Link: