CS5368(2005) 데이터 시트보기 (PDF) - Cirrus Logic
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CS5368 Datasheet PDF : 39 Pages
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CS5368
SWITCHING SPECIFICATIONS - CONTROL PORT - SPI TIMING
(VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, CDOUT CL = 30 pF)
Parameter
CCLK Clock Frequency
RST Rising Edge to CS Falling
CS Falling to CCLK Edge
CS High Time Between Transmissions
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time1
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN2
Fall Time of CCLK and CDIN3
Symbol
Min
fsck
0
tsrs
20
tcss
20
tcsh
1.0
tscl
66
tsch
66
tdsu
40
tdh
15
tpd
-
tr1
-
tf1
-
tr2
-
tf2
-
Max
Units
6.0
MHz
-
ns
-
ns
-
µs
-
ns
-
ns
-
ns
-
ns
50
ns
25
ns
25
ns
100
ns
100
ns
Notes:
1. Data must be held for sufficient time to bridge the transition time of CCLK.
2. For fsck <1 MHz
3. For fsck <1 MHz.
RST
tsrs
CS
tcss
tsch
tscl
tcsh
tr2
CCLK
tf2
tdsu tdh
CDIN
tpd
CDOUT
Figure 5. SPI Timing
DS624A1
21
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