ST72521AR7TC 데이터 시트보기 (PDF) - STMicroelectronics

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ST72521AR7TC

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE

STMicroelectronics 

ST72521M/R/AR

OPERATING CONDITIONS (Cont’d)

12.3.2 Operating Conditions with Low Voltage Detector (LVD)

Subject to general operating conditions for VDD, fCPU, and TA.

Symbol

Parameter

Conditions

Min Typ Max Unit

VIT+(LVD)

VIT-(LVD)

Vhys(LVD)

VtPOR

tg(VDD)

Reset release threshold

(VDD rise)

Reset generation threshold

(VDD fall)

LVD voltage threshold hysteresis 1)

VDD rise time 1)2)

Filtered glitch delay on VDD 1)

VD level = High in option byte

VD level = Med. in option byte

VD level = Low in option byte

VD level = High in option byte

VD level = Med. in option byte

VD level = Low in option byte

VIT+(LVD)-VIT-(LVD)

Not detected by the LVD

4.0 1)

4.2

4.5

Not Applicable

3.8

4.0 4.25 1)

Not Applicable

150 200 250

6

∝

40

V

mV

µs/V

ns

Notes:

1. Data based on characterization results, not tested in production.

2. When VtPOR is faster than 100 µs/V, the Reset signal is released after a delay of max. 42µs after VDD crosses the

VIT+(LVD) threshold.

Figure 78. LVD Startup Behaviour

5V

LVD RESET

VIT+

V DD

1.5V

0.8V

Window

t

Note: When the LVD is enabled, the MCU reaches its authorized operating voltage from a reset state.

However, in some devices, the reset state is released when VDD is approximately between 0.8V and 1.5V.

As a consequence, the I/Os may toggle when VDD is within this window.

This may be an issue especially for applications where the MCU drives power components.

Because Flash write access is impossible within this window, the Flash memory contents will not be cor-

rupted.

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