PSD932F2-A-20UI 데이터 시트보기 (PDF) - STMicroelectronics

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PSD932F2-A-20UI

Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs

STMicroelectronics 

PSD9XX Family

The

PSD9XX

Functional

Blocks

(cont.)

Preliminary Information

Table 33. Status During Power On Reset, Warm Reset and Power Down Mode

Port Configuration Power On Reset

Warm Reset Power Down Mode

MCU I/O

Input Mode

Input Mode

Unchanged

PLD Output

Valid after internal

PSD configuration

bits are loaded

Valid

Depend on inputs to

PLD (address are

blocked in PD mode)

Address Out

Tri-stated

Tri-stated

Not defined

Data Port

Tri-stated

Tri-stated

Tri-stated

Register

PMMR0, 2

VM Register*

All other registers

Power On Reset

Cleared to “0”

Initialized based on

the selection in

PSDsoft

Configuration Menu.

Cleared to “0”

Warm Reset Power Down Mode

Unchanged

Unchanged

Initialized based on Unchanged

the selection in

PSDsoft

Configuration Menu.

Cleared to “0”

Unchanged

*SR_cod bit in the VM Register are always cleared to zero on power on or warm reset.

**

9.5.3.4 Reset of Flash Erase and Programming Cycles (PSD934F2 and PSD954F2)

An external reset on the RESET pin will also reset the internal Flash memory state

machine. When the Flash is in programming or erase mode, the RESET pin will terminate

the programming or erase operation and return the Flash back to read mode in tNLNH-A

(minimum 25 µs) time.

9.6 Programming In-Circuit using the JTAG Interface

The JTAG interface on the PSD9XX can be enabled on Port C (see Table 34). All

memory (Flash and Secondary Flash Block), PLD logic, and PSD configuration bits may be

programmed through the JTAG interface. A blank part can be mounted on a printed circuit

board and programmed using JTAG.

The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional

signals, TSTAT and TERR, are optional JTAG extensions used to speed up program and

erase operations.

By default, on a blank PSD (as shipped from factory or after erasure), four pins on Port C

are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO.

See Application Note 54 for more details on JTAG In-System-Programming.

Table 34. JTAG Port Signals

Port C Pin JTAG Signals

PC0

TMS

PC1

TCK

PC3

TSTAT

PC4

TERR

PC5

TDI

PC6

TDO

Description

Mode Select

Clock

Status

Error Flag

Serial Data In

Serial Data Out

60

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