ST7MC2N6T3 데이터 시트보기 (PDF) - STMicroelectronics
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ST7MC2N6T3
STMicroelectronics
ST7MC2N6T3 Datasheet PDF : 309 Pages
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ST7MC1xx/ST7MC2xx
INTERRUPTS (Cont’d)
Table 7. Dedicated Interrupt Instruction Set
Instruction
New Description
Function/Example
I1 H I0 N Z C
HALT
Entering Halt mode
1
0
IRET
Interrupt routine return
Pop CC, A, X, PC
I1 H I0 N Z C
JRM
Jump if I1:0=11 (level 3)
I1:0=11 ?
JRNM
Jump if I1:0<>11
I1:0<>11 ?
POP CC
Pop CC from the Stack
Mem => CC
I1 H I0 N Z C
RIM
Enable interrupt (level 0 set)
Load 10 in I1:0 of CC
1
0
SIM
Disable interrupt (level 3 set)
Load 11 in I1:0 of CC
1
1
TRAP
Software trap
Software NMI
1
1
WFI
Wait for interrupt
1
0
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current
software priority up to the next IRET instruction or one of the previously mentioned instructions.
Table 8. Interrupt Mapping
N°
Source
Block
Description
Register
Label
Priority
Order
Exit
from
Halt1)
Address
Vector
RESET
TRAP
Reset
Software interrupt
yes FFFEh-FFFFh
N/A
no FFFCh-FFFDh
0
MCES
Motor Control Emergency Stop
or Speed error interrupt
MISR
MCRC
no
Highest
FFFAh-FFFBh
1
MCC/RTC Main clock controller time base interrupt
CSS
Safe oscillator activation interrupt
MCCSR
SICSR
Priority
yes
FFF8h-FFF9h
2
ei0
External interrupt port
yes FFF6h-FFF7h
3
ei1
External interrupt port
N/A
yes FFF4h-FFF5h
4
ei2
External interrupt port
yes FFF2h-FFF3h
5
Event U or Current Loop or Sampling Out MISR/MCONF
no FFF0h-FFF1h
6
MTC
Event R or Event Z
7
Event C or Event D
MISR
no FFEEh-FFEFh
no FFECh-FFEDh
8
SPI
SPI peripheral interrupts
SPICSR
yes FFEAh-FFEBh
9
TIMER A TIMER A peripheral interrupts
TASR
no FFE8h-FFE9h
10 TIMER B TIMER B peripheral interrupts
11 LINSCI™ LINSCI™ Peripheral interrupts
12
AVD/
ADC
Auxiliary Voltage detector interrupt
ADC End of conversion interrupt
TBSR
SCISR
SICSR
ADCSR
no
Lowest no
Priority
yes
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
13
PWM ART
PWM ART overflow interrupt
PWM ART input capture interrupts
ARTCSR
ARTICCSR
no FFE0h-FFE1h
Note 1. Valid for Halt and Active-halt modes except for the MCC/RTC or CSS interrupt source which exits from Active-
halt mode only.
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