DSPIC33FJ32GP302T-I/SO 데이터 시트보기 (PDF) - Microchip Technology
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DSPIC33FJ32GP302T-I/SO Datasheet PDF : 402 Pages
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dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 8-3: DMAxSTA: DMA CHANNEL x RAM START ADDRESS REGISTER A(1)
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
STA<15:8>
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
STA<7:0>
R/W-0
R/W-0
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
STA<15:0>: Primary DMA RAM Start Address bits (source or destination)
Note 1: A read of this address register returns the current contents of the DMA RAM Address register, not the
contents written to STA<15:0>. If the channel is enabled (i.e., active), writes to this register may result in
unpredictable behavior of the DMA channel and should be avoided.
REGISTER 8-4: DMAxSTB: DMA CHANNEL x RAM START ADDRESS REGISTER B(1)
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
STB<15:8>
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
STB<7:0>
R/W-0
R/W-0
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
STB<15:0>: Secondary DMA RAM Start Address bits (source or destination)
Note 1: A read of this address register returns the current contents of the DMA RAM Address register, not the con-
tents written to STB<15:0>. If the channel is enabled (i.e., active), writes to this register may result in
unpredictable behavior of the DMA channel and should be avoided.
DS70292D-page 134
Preliminary
2009 Microchip Technology Inc.
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