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ST72F324J2TCRS 데이터 시트보기 (PDF) - STMicroelectronics

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ST72F324J2TCRS Datasheet PDF : 194 Pages
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ST72324xx-Auto
On-chip peripherals
Table 65. SCIBRR register description (continued)
Bit Name
Function
SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 and SCP0 bits, define the total division
applied to the bus clock to yield the transmit rate clock in conventional baud rate
generator mode.
000: TR dividing factor = 1
5:3 SCT[2:0] 001: TR dividing factor = 2
010: TR dividing factor = 4
011: TR dividing factor = 8
100: TR dividing factor = 16
101: TR dividing factor = 32
110: TR dividing factor = 64
) 111: TR dividing factor = 128
t(s SCI Receiver rate divisor
bsolete Produc 2:0 SCR[2:0]
These 3 bits, in conjunction with the SCP[1:0] bits, define the total division applied
to the bus clock to yield the receive rate clock in conventional baud rate generator
mode.
000: RR dividing factor = 1
001: RR dividing factor = 2
010: RR dividing factor = 4
011: RR dividing factor = 8
100: RR dividing factor = 16
101: RR dividing factor = 32
110: RR dividing factor = 64
111: RR dividing factor = 128
) - O SCI Extended Receive Prescaler Division Register (SCIERPR)
t(s This register is used to set the Extended Prescaler rate division factor for the receive circuit.
duc SCIERPR
Reset value: 0000 0000 (00h)
ro 7
6
5
4
3
2
1
0
te P ERPR[7:0]
le R/W
Obso Table 66. SCIERPR register description
Bit Name
Function
8-bit Extended Receive Prescaler Register
7:0 ERPR[7:0]
The extended baud rate generator is activated when a value different from 00h
is stored in this register. Therefore the clock frequency issued from the 16
divider (see Figure 57) is divided by the binary factor set in the SCIERPR
register (in the range 1 to 255).
The extended baud rate generator is not used after a reset.
SCI Extended Transmit Prescaler Division Register (SCIETPR)
This register is used to set the External Prescaler rate division factor for the transmit circuit.
Doc ID 13841 Rev 1
129/193

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