C8051F521A-IM 데이터 시트보기 (PDF) - Silicon Laboratories
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C8051F521A-IM Datasheet PDF : 221 Pages
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C8051F52x/F53x
Table 3.4. Pin Definitions for the C8051F53x and C805153xA (TSSOP 20) (Continued)
Name Pin Numbers Type Description
VREGIN
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2/
‘F53xA ‘F53x
‘F53x-C
7
7
On-Chip Voltage Regulator Input.
8
8 D I/O or Port 1.7. See Port I/O Section for a complete description.
A In
9
9 D I/O or Port 1.6. See Port I/O Section for a complete description.
A In
10 10 D I/O or Port 1.5. See Port I/O Section for a complete description.
A In
11 11 D I/O or Port 1.4. See Port I/O Section for a complete description.
A In
12 12 D I/O or Port 1.3. See Port I/O Section for a complete description.
A In
13 13 D I/O or Port 1.2. See Port I/O Section for a complete description.
A In
CNVSTR
D In External Converter start input for the ADC0, see Section “4. 12-
Bit ADC (ADC0)” on page 52 for a complete description.
P1.1
P1.0/
14 14 D I/O or Port 1.1. See Port I/O Section for a complete description.
A In
15 15 D I/O or Port 1.0. See Port I/O Section for a complete description.
A In
XTAL2
D I/O
External Clock Output. For an external crystal or resonator, this
pin is the excitation driver. This pin is the external clock input for
CMOS, capacitor, or RC oscillator configurations. See Section
“14. Oscillators” on page 135.
P0.7/
XTAL1
P0.6/
16 16 D I/O or Port 0.7. See Port I/O Section for a complete description.
A In
External Clock Input. This pin is the external oscillator return for
A In a crystal or resonator. Section “14. Oscillators” on page 135.
17 17 D I/O or Port 0.6. See Port I/O Section for a complete description.
A In
C2D
D I/O Bi-directional data signal for the C2 Debug Interface.
P0.5/RX* 18 — D I/O or Port 0.5. See Port I/O Section for a complete description.
A In
P0.5
— 18 D I/O or Port 0.5. See Port I/O Section for a complete description.
A In
*Note: Please refer to Section “20. Device Specific Behavior” on page 210.
Rev. 1.4
41
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