C8051F521A-IM 데이터 시트보기 (PDF) - Silicon Laboratories

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C8051F521A-IM

8/4/2 kB ISP Flash MCU Family

Silicon Laboratories 

C8051F52x/F53x

Figure 3.6. TSSOP-20 Landing Diagram

Table 3.6. TSSOP-20 Landing Diagram Dimensions

Symbol

Min

Max

C

5.80

5.90

E

0.65 BSC.

X1

0.35

0.45

Y1

1.35

1.45

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. This land pattern design is based on the IPC-7351 guidelines.

Solder Mask Design

3. All metal pads are to be non-solder mask defined (NSMD). Clearance

between the solder mask and the metal pad is to be 60 µm minimum,

all the way around the pad.

Stencil Design

4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal

walls should be used to assure good solder paste release.

5. The stencil thickness should be 0.125 mm (5 mils).

6. The ratio of stencil aperture to land pad size should be 1:1 for all

perimeter pads.

Card Assembly

7. A No-Clean, Type-3 solder paste is recommended.

8. The recommended card reflow profile is per the JEDEC/IPC J-STD-

020 specification for Small Body Components.

44

Rev. 1.4

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