ELECTRICAL SPECIFICATIONS
4.5.9 IDE INTERFACE
Figure 4-13, Figure 4-14 and Table 4-18 lists the
AC characteristics of the IDE interface.
Figure 4-13. IDE PIO timing diagram
CS#,DA[2:0]
DIOR#,DIOW#
DD[15:0]
IORDY
Tsetup
Thold
Figure 4-14. IDE DMA timing diagram
CS#
REQ
ACK#
DIOR#,DIOW#
DD[15:0] read
DD[15:0] write
Tsetup
Thold
Name
Tsetup
Thold
Table 4-18. IDE Interface Timing
Parameters
Min
DD[15:0] setup to PIOR#/SIOR# falling
15
DD[15:0} hold to PIOR#/SIOR# falling
0
Max
Units
-
ns
-
ns
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