PSD511B1-C-90UI Просмотр технического описания (PDF) - STMicroelectronics
Номер в каталоге
Компоненты Описание
производитель
PSD511B1-C-90UI Datasheet PDF : 153 Pages
| |||
PSD5XX Family
AC/DC Parameters – ZPLD Timing Parameters (5 V ± 10% Versions)
Counter/Timer Timing (5 V ± 10%)
Symbol
fMAX
t CHCL
t CLCH
t CHPV
t CHPV1
t LVCH
t LVCH1
t MIN
Parameter
Maximum Frequency
Clock High Time
Clock Low Time
Clock to Output Delay
Clock to Watchdog
Output Dealy
Input Setup Time
Relative to Rising
Clock Edge
Input Setup Time
Relative to Rising
Clock Edge
Minimum Clock
Period
Conditions
Pin Input
PLD
Combinatorial
Input
1/fMAX
-70
Min Max
36.00
10
10
28
-90**
Min Max
30.00
12
12
30
-15
ZPLD_TURBO
Min Max OFF* Unit
22.00
0
MHz
15
0
ns
15
0
ns
33
0
ns
50
50
58
Add 10 ns
15
17
20
Add 10
(Note 2) ns
25
27
31
(Note 2) ns
28
33
45
0
ns
Interrupt Timing (5 V ± 10%)
Symbol
t IVIV
t RXIX
t ILIL
t RLQV
Parameter
Interrupt Request
Input to Interrupt
Output
Read Vector to
Interrupt Request
Clear
Interrupt Request
Minimum Pulse
Width
RD to Data Valid
Interrupt Controller
Conditions
-70
-90**
-15
ZPLD_TURBO
Min Max Min Max Min Max OFF* Unit
(Note 3)
40
50
65
0
ns
30
40
55
0
ns
(Note 1)
18
20
35
32
38
45
0
ns
0
ns
NOTES: 1. Read to Data Valid of the Interrupt Request Latch and Interrupt Priority Status. RD timing has the same timing as PSEN, DS,
LDS, UDS signals.
2. For inputs which use PPLD only.
3. This timing is only valid when read to the interrupt request latch and priority status latch are not valid.
**If ZPLD_TURBO is off and the ZPLD is operating above 15 MHz, there is no need to add 10 ns to the timing parameters.
**The -90 speed is available only on Industrial Temperature Range product.
119
Share Link: 