STM32F100RB(2010) Просмотр технического описания (PDF) - STMicroelectronics

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производитель

STM32F100RB
(Rev.:2010)

Low & medium-density value line, advanced ARM-based 32-bit MCU with 16 to 128 KB Flash, 12 timers, ADC, DAC & 8 comm interfaces

STMicroelectronics 

Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

negative currents.

Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in

Section 5.3.12 does not affect the ADC accuracy.

Figure 31. ADC accuracy characteristics

[1LSBIDEAL

=VREF+

4096

(or

VDDA depending

4096

on

package)]

EG

4095

4094

4093

7

6

5

EO

4

3

2

1

(2)

ET

(3)

(1)

EL

ED

1 LSBIDEAL

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation line

ET=Total Unadjusted Error: maximum deviation

between the actual and the ideal transfer curves.

EO=Offset Error: deviation between the first actual

transition and the first ideal one.

EG=Gain Error: deviation between the last ideal

transition and the last actual one.

ED=Differential Linearity Error: maximum deviation

between actual steps and the ideal one.

EL=Integral Linearity Error: maximum deviation

between any actual transition and the end point

correlation line.

0

1234567

VSSA

4093 4094 4095 4096

VDDA

ai14395b

Figure 32. Typical connection diagram using the ADC

RAIN(1) AINx

VAIN

Cparasitic

VDD

VT

0.6 V

VT

0.6 V

STM32F10xxx

Sample and hold ADC

converter

RADC(1) 12-bit

converter

IL±1 µA

CADC(1)

ai14139d

1. Refer to Table 41 for the values of RAIN, RADC and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy

this, fADC should be reduced.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 33 or Figure 34,

depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be

ceramic (good quality). They should be placed them as close as possible to the chip.

68/84

Doc ID 16455 Rev 2

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