PIC16C925/926
FIGURE 15-6:
OSC1
CLKOUT AND I/O TIMING
Q4
Q1
10
CLKOUT
I/O Pin
(input)
13
14
17
I/O Pin
(output)
old value
Note:
20, 21
Refer to Figure 15-4 for load conditions.
Q2
19 18
15
Q3
11
12
16
new value
TABLE 15-4: CLKOUT AND I/O TIMING REQUIREMENTS
Parameter
No.
Symbol
Characteristic
Min
Typ†
Max
Units Conditions
10
TosH2ckL OSC1↑ to CLKOUT↓
—
75
200
ns
11
TosH2ckH OSC1↑ to CLKOUT↑
—
75
200
ns
12
TckR
CLKOUT rise time
—
35
100
ns
13
TckF
CLKOUT fall time
—
35
100
ns
14
TckL2ioV CLKOUT ↓ to Port out valid
—
— 0.5TCY + 20 ns
15
TioV2ckH Port in valid before CLKOUT ↑
Tosc + 200 —
—
ns
16
TckH2ioI Port in hold after CLKOUT ↑
0
—
—
ns
17
TosH2ioV OSC1↑ (Q1 cycle) to
Port out valid
—
50
150
ns
18
TosH2ioI OSC1↑ (Q2 cycle) to PIC16C925/926
100
—
—
ns
Port input invalid
PIC16LC925/926
200
—
—
ns
(I/O in hold time)
19
TioV2osH Port input valid to OSC1↑ (I/O in setup time)
0
—
—
ns
20
TioR
Port output rise time PIC16C925/926
—
10
40
ns
PIC16LC925/926
—
—
80
ns
21
TioF
Port output fall time
PIC16C925/926
—
10
40
ns
PIC16LC925/926
—
—
80
ns
22††
Tinp
INT pin high or low time
TCY
—
—
ns
23††
Trbp
RB7:RB4 change INT high or low time
TCY
—
—
ns
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
DS39544A-page 148
Preliminary
2001 Microchip Technology Inc.