PIC16C925T-S/CL 查看數據表（PDF） - Microchip Technology

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PIC16C925T-S/CL

64/68-Pin CMOS Microcontrollers with LCD Driver

Microchip Technology 

PIC16C925/926

2.3.4 PIE1 REGISTER

This register contains the individual enable bits for the

peripheral interrupts.

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

REGISTER 2-4:

PIE1 REGISTER (ADDRESS 8Ch)

R/W-0 R/W-0

U-0

U-0

LCDIE

ADIE

—

—

bit 7

R/W-0

SSPIE

R/W-0

CCP1IE

R/W-0

TMR2IE

R/W-0

TMR1IE

bit 0

bit 7

bit 6

bit 5-4

bit 3

bit 2

bit 1

bit 0

LCDIE: LCD Interrupt Enable bit

1 = Enables the LCD interrupt

0 = Disables the LCD interrupt

ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D interrupt

0 = Disables the A/D interrupt

Unimplemented: Read as ‘0’

SSPIE: Synchronous Serial Port Interrupt Enable bit

1 = Enables the SSP interrupt

0 = Disables the SSP interrupt

CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt

TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

DS39544A-page 22

Preliminary

 2001 Microchip Technology Inc.

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