STPCI2 查看數據表（PDF） - STMicroelectronics

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STPCI2

X86 CORE PC COMPATIBLE SYSTEM-ON-CHIP FOR TERMINALS

STMicroelectronics 

STPC® ATLAS

The figure below describes a complete

implementation of the external glue logic for DMA

Request time-multiplexing and DMA Acknowledge

demultiplexing. Like for the interrupt lines, this

logic can be simplified when only few DMA

channels are used in the application.

This glue logic is not needed in Local bus mode as

it does not support DMA transfers.

Figure 6-12. Typical DMA multiplexing and demultiplexing

74x153

ISA, Refresh

DRQ[0]

1C0

ISA, PIO

ISA, FDC

DRQ[1]

DRQ[2]

1C1 1Y

1C2

DREQ_MUX[0]

ISA, PIO

DRQ[3]

1C3

Slave DMAC

DRQ[4]

2C0

ISA

ISA

DRQ[5]

DRQ[6]

2C1 2Y

2C2

DREQ_MUX[1]

ISA

DRQ[7]

2C3

t(s) A

B

uc 1G 2G

rod ISA_CLK2X

P ISA_CLK

bsolete DMA_ENC[0]

O DMA_ENC[1]

t(s) - DMA_ENC[2]

74x138

Y0#

Y1#

Y2#

A Y3#

B Y4#

C Y5#

Y6#

Y7#

DACK0#

DACK1#

DACK2#

DACK3#

DACK5#

DACK6#

DACK7#

duc G1

Obsolete Pro G2A G2B

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