STPCI2 查看數據表（PDF） - STMicroelectronics

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STPCI2

X86 CORE PC COMPATIBLE SYSTEM-ON-CHIP FOR TERMINALS

STMicroelectronics 

STPC® ATLAS

6.3.13. JTAG INTERFACE

The STPC integrates a JTAG interface for scan-

chain and on-board testing. The only external

Figure 6-19. Typical JTAG implementation

device needed are the pull up resistors. Figure 6-

19 describes a typical implementation using these

devices.

3V3 3V3 3V3 3V3

Connector

10 9

TCLK

87

TDO

ct(s) TMS

rodu TDI

lete P TRST

65

43

21

Obso STPC

t(s) - 6.4. PLACE AND ROUTE RECOMMENDATIONS

uc 6.4.1. GENERAL RECOMMENDATIONS

rod Some STPC Interfaces run at high speed and

P need to be carefully routed or even shielded like:

te 1) Memory Interface

le 2) PCI bus

3) Graphics and video interfaces

o 4) 14 MHz oscillator stage

bs All clock signals have to be routed first and

Oshielded for speeds of 27MHz or higher. The high

All the analog noise-sensitive signals have to be

routed in a separate area and hence can be routed

indepedently.

6.4.2. PLL DEFINITION AND IMPLIMENTATION

PLLs are analog cells which supply the internal

STPC Clocks. To get the cleanest clock, the jitter

on the power supply must be reduced as much as

possible. This will result in a more stable system.

Each of the integrated PLL has a dedicated power

pin so a single power plane for all of these PLLs, or

one wire for each, or any solution in between

speed signals follow the same constraints, as for which help the layout of the board can be used.

the memory and PCI control signals.

Powering these pins with one Ferrite +

The next interfaces to be routed are Memory, PCI,

and Video/graphics.

capacitances is enough. We recommend at least 2

capacitances: one 'big' (few uF) for power storage,

and one or 2 smalls (100nF + 1nF) for noise

filtering.

89/108

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