STRAP OPTION
2.1.6 HCLK PLL STRAP REGISTER 0 INDEX 5FH (HCLK_STRAP0)
Bits 5-0 of this register reflect the status of pins MD[26:21] respectively.
They are use by the chip as follows:
Bits 7-6, Reserved.
Bits 5-3, These pins reflect the value sampled on MD[26:24] pins respectively and control the Host clock
frequency synthesizer.
Bit 2-1, Reserved.
Bit 0, Reserved.
This register defaults to the values sampled on above pins after reset.
16/55
Issue 1.1