STPCI01 查看數據表（PDF） - STMicroelectronics

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STPCI01

PC Compatible Embedded Microprocessor

STMicroelectronics 

PIN DESCRIPTION

Table 3-2. Definition of Signal Pins

Signal Name

Dir

Description

Qty

RMRTCCS#*

O

ROM / RTC Chip Select

1

GPIOCS#*

I/O

General Purpose Chip Select

1

IRQ_MUX[3:0]*

I

Multiplexed Interrupt Request

4

DACK_ENC[2:0]*

O

DMA Acknowledge

3

DREQ_MUX[1:0]*

I

Multiplexed DMA Request

2

TC*

O

ISA Terminal Count

1

KEYBOARD & MOUSE INTERFACE

KBDATA*, MDATA*

I

Keyboard & Mouse Data Line

2

KBCLK*, MCLK*

O

Keyboard & Mouse Clock Line

2

SERIAL INTERFACE (SERIAL 1 COMBINED WITH TFT INTERFACE / SERIAL 2 COMBINED WITH IPC )

SIN1*, SIN2*

I

Serial Data In (Serial 1, 2)

2

SOUT1*, SOUT2*

O

Serial Data Out (Serial 1, 2)

2

CTS1#*, CTS2#*

I

Clear To Send (Serial 1, 2)

2

RTS1#*, RTS2#*

O

Request To Send (Serial 1, 2)

2

DSR1#*, DSR2#*

I

Data Set Ready (Serial 1, 2)

2

DTR1#*, DTR2#*

O

Data Terminal Ready (Serial 1,2)

2

DCD1#*, DCD2#*

I

Data Carrier Detect (Serial 1, 2)

2

RI1#*, RI2#*

I

Ring Indicator (Serial 1, 2)

2

PARALLEL PORT (COMBINED WITH ISA BUS AND IPC)

PE*

I

Paper End

1

SLCT*

I

SELECT

1

BUSY#*

I

BUSY

1

ERR#*

I

ERROR

1

ACK#*

I

Acknowledge

1

PDDIR#*

O

Parallel Device Direction

1

STROB E#*

O

PCS / STROBE#

1

INIT#*

O

INIT

1

AUTPFDX#*

O

Automatic Line Feed

1

SLCTIN#*

O

SELECT IN

1

PPD[7:0]*

I/O

Data Bus

8

PCMCIA INTERFACE (COMBINED WITH PCI / CARDBUS)

RESET*

O

Reset

1

A[25:0]*

O

Address Bus

26

D[15:0]*

I/O

Data Bus

16

IORD#*, IOWR#*

O

I/O Read and Write

2

DREQ#* / WP* / IOIS16#*

I

DMA Request // Write Protect // I/O Size is 16 bit

1

BVD1*, BVD2*

I

Battery Voltage Detect

2

READY#*/BUSY#*/IREQ#*

I

Ready / Busy // Interrupt Request

1

WAIT#*

I

Wait

1

INPACK#*

I

Input Port Acknowledge

1

OE#* / TCw*

O

Output Enable // DMA Terminal Count

1

WE#* / TCr*

O

Write Enable // DMA Terminal Count

1

DACK* / REG#*

O

DMA Acknowledge // Register

1

CD1#*, CD2#*

I

Card Detect

2

Issue 1.1

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