CL-PS7500FE 查看數據表（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

16.28 Data Control Register (DCTL): Address 0xF

The horizontal display width is also defined in this register, and should be programmed to be the number

of words of data in a displayed raster. It must be programmed in most configurations of the device, as it

inhibits a DMA request near the end of a raster, when there are enough words in the video FIFO for that

raster. The request is uninhibited after the HSYNC at the start of the next raster. When driving a dual-panel

LCD screen, this register must be programmed with twice the number of words in a displayed raster.

DCTL[14] (Hdis) must normally be programmed to ‘0’. If DCTL[14] is programmed to one, the inhibition of

DMA requests is disabled.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1111

0 0 01

XX

XXXXXXXXXX

NOTE: Bits 19:16 must be set to ‘0001’ (binary).

HDWR value

SnA — must be synchronous (1)

Hdis

1 disable

0 enable

16.29 Sound Frequency Register (SFR): Address 0xB0

This 8-bit register specifies the byte sample rate of the sound data. It is defined in units of 1 µs. See

Chapter 13 for more details.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1011 0000

XXXXXXXX

SFR value

If a sample rate of N µs is required, N − 2 should be programmed into SFR. N can have any value between

3 and 256.

154

THE VIDEO SOUND AND PROGRAMMER’S MODEL

ADVANCE DATA BOOK v2.0

June 1997

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