CL-PS7500FE 查看數據表（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

The register bank also contains logic for register-forwarding, allowing the result of one calculation to be

used directly as the source for the next.

17.1.5 Arithmetic Unit

The arithmetic unit has a four-stage pipeline (Prepare, Calculate, Align, and Round) and can speculatively

execute instructions up to, but not including, register writeback. Writeback can only occur once the instruc-

tion has been arbitrated with the ARM CPU.

An unusual feature of the pipeline is that each of the pipeline stages is offset by one half-cycle from the

previous stage, allowing some instructions to traverse the pipeline in 2 cycles.

The calculate stage includes a 67-bit adder, iterative array multiplier and divide unit. Fast barrel shifters

are used for pre-alignment and post-normalization.

Arithmetic operations are normally performed asynchronously to the ARM instruction stream so that an

instruction is arbitrated with the CPU before the FPA has detected whether an exception will occur. Arith-

metic exceptions are therefore normally imprecise. If precise exceptions are required (for example, in

debugging), a mode bit (the SO bit in the FPSR) can be set. This forces arbitration to be delayed until

the arithmetic operation completes, at the expense of a reduction in performance.

158

FPA COPROCESSOR MACROCELL

ADVANCE DATA BOOK v2.0

June 1997

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