CL-PS7500FE 查看數據表（PDF） - Cirrus Logic
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CL-PS7500FE Datasheet PDF : 251 Pages
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CL-PS7500FE
System-on-a-Chip for Internet Appliance
Table 22-7. Module 8-MHz I/O Timing
Symbol Parameter
40 MHz
MIN MAX
tbds1
DATA setup to nBLI falling
0
tbdh1
DATA hold from nBLI falling
2
tcsl_ms
I_OCLK falling to nMSCS falling
18
tcsh_ms
I_OCLK falling to nMSCS rising
22
tiornwh
I_OCLK falling to IORNW rising
14
tiornwl
tbd1 a
tbd2b, c
I_OCLK falling to IORNW falling
I_OCLK rising to BD write data valid
I_OCLK rising to BD write data valid
14
0
102
133
150
tbd2
I_OCLK rising to BD write data valid
164
181
tniorql
I_OCLK rising to nIORQ falling
15
tniorqh
I_OCLK rising to nIORQ rising
15
tr8ml
I_OCLK rising to REF8M falling
13
tr8mh
I_OCLK rising to REF8M rising
12
tgts
setup of nIOGT to I_OCLK rising
0
tgth
tadd1 d
tadd2e, c
tadd2e, f
hold of nIOGT to I_OCLK rising
LA[28:0] changing after I_OCLK rising before start
LA[28:0] changing after I_OCLK rising after end
LA[28:0] changing after I_OCLK rising after end
5
0
143
74
89
105
120
a Synchronization penalty is between 0 and 3 I_OCLK cycles.
b Delay includes 4 MEMCLK cycles.
c Timings refer to the case where ASTCR bit = 0.
d Synchronization penalty is between 0 and 4 I_OCLK cycles.
e Delay includes 2 MEMCLK cycles.
f Timings refer to the worst case where ASTCR bit = 1 (see Appendix C ).
56 MHz
MIN
0
2
0
133
164
0
5
0
74
105
MAX
18
22
14
14
102
150
181
15
15
13
12
143
89
120
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
212
ELECTRICAL SPECIFICATIONS
ADVANCE DATA BOOK v2.0
June 1997
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