CL-PS7500FE 查看數據表（PDF） - Cirrus Logic
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CL-PS7500FE Datasheet PDF : 251 Pages
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CL-PS7500FE
System-on-a-Chip for Internet Appliance
Table 22-8. 16-MHz I/O Timing
Symbol Parameter
tnmxl
tnmxh
txls
txlh
tc16l
tc16h
tbdh
tbds
tiornwh
tiornwl
tcsl_pc a
tcsh_pca
trds
trdh
tbd2b, c
tbd2b, d
tbd3 e
tniorl
tniorh
tnoh1
tnol1
tnoh2
tnol2
tnwbeh
tnwbel
trbel
trbeh
tniowl
tniowh
tdu
tadd3 f
tduh
tadd2c, g
tadd2d, g
nXIPMUX16 falling to upper data output on BD[15:0]
nXIPMUX16 rising to lower data output on BD[15:0]
DATA setup to nXIPLATCH falling
DATA hold from nXIPLATCH falling
I_OCLK rising to CLK16 falling
I_OCLK rising to CLK16 rising
DATA hold from I_OCLK rising
DATA setup to I_OCLK rising
I_OCLK falling to IORNW rising
I_OCLK rising to IORNW falling
I_OCLK rising to PC I/O chip select falling
I_OCLK rising to PC I/O chip select rising
READY setup to I_OCLK rising
READY hold from I_OCLK rising
I_OCLK rising to BD write data valid
I_OCLK rising to BD write data valid
I_OCLK rising to BD write data valid
I_OCLK rising to nIOR falling
I_OCLK rising to nIOR rising
I_OCLK rising to nBLO rising, read
I_OCLK rising to nBLO falling, read
MEMCLK rising to nBLO rising, write
MEMCLK rising to nBLO falling, write
I_OCLK falling to nWBE rising
I_OCLK rising to nWBE falling
MEMCLK rising to nRBE falling
MEMCLK rising to nRBE rising
I_OCLK rising to nIOW falling
I_OCLK rising to nIOW rising
MEMCLK rising to D[31:16] valid
LA[28:0] changing after I_OCLK rising before start
MEMCLK rising to D[31:16] invalid
LA[28:0] changing after I_OCLK rising at end
LA[28:0] changing after I_OCLK rising at end
214
ELECTRICAL SPECIFICATIONS
40 MHz
MIN MAX
6
5
1
2
12
12
10
0
13
16
20
22
0
8
133 150
164 181
0
40
16
16
18
20
22
19
20
17
16
21
17
16
35
0
82
10
74
89
105 120
56 MHz
MIN MAX
6
5
1
2
12
12
10
0
14
16
20
22
0
8
133
150
164
181
0
40
16
16
18
20
22
19
20
17
16
21
17
16
35
0
82
10
74
89
105
120
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADVANCE DATA BOOK v2.0
June 1997
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