CL-PS7500FE 查看數據表（PDF） - Cirrus Logic

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产品描述 (功能)

生产厂家

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

Table 22-10. Serial Sound Output Timing

Symbol

tsdo

tsdoj

Parameter

SDCLK falling to SDO valid (normal format)

SDCLK falling to SDO valid (Japanese format)

40 MHz

MIN MAX

0

5

0

5

56 MHz

MIN MAX

0

5

0

5

Units

ns

ns

SDCLK

SDO

ts d o

Bit 1

lsb

WS

msb

left channel

Bit 1

lsb

msb

right channel

Figure 22-25. Serial Sound Output Timing (Normal Format)

SDCLK

SDO

ts d o

Bit 1

lsb

WS

msb

left channel

Bit 1

lsb

msb

right channel

Figure 22-26. Serial Sound Output Timing (Japanese Format)

June 1997

ADVANCE DATA BOOK v2.0

ELECTRICAL SPECIFICATIONS

221

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