CL-PS7500FE 查看數據表（PDF） - Cirrus Logic
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CL-PS7500FE Datasheet PDF : 251 Pages
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CL-PS7500FE
System-on-a-Chip for Internet Appliance
Appendix A
A.Initialization and Boot Sequence
1. Introduction
CL-PS7500FE is designed to operate with 16- or 32-bit-wide memory systems. To avoid a hardware
selection mechanism, the CL-PS7500FE is designed to always power-up with ROMCR0[6] set to ‘1’, then
the device expects to receive the first instructions from a 16-bit-wide ROM bank. For a system that is actu-
ally using 16-bit-wide ROM, no special action is required. For a system that uses 32-bit-wide ROM, a soft-
ware solution is required for the device to boot successfully.
A sample method of programming the first locations of ROM to successfully boot the device is described
in Section 1. This example assumes that the reset vector is located at physical memory address zero.
2. Sample Boot Sequence
The processor starts executing code from physical address 0. As CL-PS7500FE is initially configured to
operate with a 16-bit-wide ROM, it fetches the lower half-word of the first instruction from the lower 16 bits
of address 0; the upper half-word of the instruction is fetched from the lower 16 bits of address 4.
If these first two locations are programmed with instructions to load the PC with the reset and undefined
instruction vectors, then the combination of the lower half-words from the first and second location always
create an instruction with a ‘never-true’ condition code, therefore execution drops through to the next
instruction. This is true for all LDR PC instructions in the exception table. Table A-1 is the exception table
occupying the first eight locations in ROM. This vector table resides at physical address 0.
Table A-1. Vector Table
Address
0
4
8
C
10
14
18
1C
Instruction
LDR PC, RESET_VEC
LDR PC, UNDEF_VEC
LDR PC, SWI_VEC
LDR PC, PREF_VEC
LDR PC, DATA_VEC
LDR PC, RES_VEC
LDR PC, IRQ_VEC
LDR PC, FIQ_VEC
June 1997
ADVANCE DATA BOOK v2.0
227
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