CL-PS7500FE 查看數據表（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

The CL-PS7500FE can control a 32- or 16-bit-wide memory system. The width of each bank of ROM or

DRAM is selectable by programming appropriate register bits. Fast page mode or EDO DRAMs are sup-

ported.

A DRAM controller is included that can directly drive up to four banks of DRAM. Four nRAS strobes indi-

vidually select one of the four banks, and four nCAS strobes provide individual byte selection. The DRAM

address multiplexing option provided allows a wide variety of DRAM sizes to be used – from 256 Kbytes

to beyond 16 Mbytes. Up to 256 page mode transfers can occur in one sequential burst. When configured

for operation with a 16-bit-DRAM system, the DRAM controller converts the access into two DRAM cycles

to access the two halves of the 32-bit word. Byte transfers only take one DRAM access cycle, even in 16-

bit mode.

A programmable register allows one of four DRAM refresh rates to be selected. In addition, a register is

provided to enable direct software control of the nCAS and nRAS lines for setting DRAM into a self-refresh

state.

A ROM controller supports two 16-Mbyte banks of ROM with individually programmable read cycle tim-

ings. Support is provided for burst mode reads. Each ROM bank can be programmed to operate in 16-bit-

wide mode and, like the DRAM controller, converts accesses into two ROM cycles for the two halves of

the 32-bit word. The ROM controller can be programmed to allow write cycles through this interface, allow-

ing FLASH to be programmed.

3.6.1 DMA

Three fully programmable DMA channels are included, for video, cursor, and sound data. The DMA con-

troller includes additional support for dual-panel LCDs.

3.6.2 I/O Control

The I/O bus of the CL-PS7500FE is 16-bits wide, but for some types of access can be expanded to 32

bits by the use of external transceivers. The input clock I_OCLK provides a reference for the I/O sub-

system nominally 32 MHz. The I/O features of this device can be separated into three distinct cycle types:

q Simple I/O with fixed 8-MHz timings

q Module I/O with variable length 8-MHz timings

q PC bus style I/O with fixed 16-MHz timings and support for 32-bit data

Simple I/O

The Simple I/O type of access is 16-bit-only and has a selection of four different cycle speeds selectable

by address. When writing, the upper half-word of the ARM data bus is written out on the I/O bus. When

reading, the I/O bus data is read back onto the lower half-word of the ARM data bus. During these

accesses, a chip select is asserted with the appropriate nIOR/nIOW read or write strobe, based on the

8-MHz clock CLK8.

Module I/O

The Module I/O type of access is 16 bits only and timing is controlled by a handshake mechanism with

the external hardware. The signals nIORQ (output) and nIOGT (input) are used for this handshaking and

are referenced to REF8M. When writing, the upper half-word of the ARM data bus is written out on the

I/O bus. When reading, the I/O bus data is read back onto the lower half-word of the ARM data bus.

30

FUNCTIONAL DESCRIPTION

ADVANCE DATA BOOK v2.0

June 1997

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