CL-PS7500FE 查看數據表（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

During these accesses, a chip select is asserted but the nIOR/nIOW read and write strobes are not used,

although the IORNW signal is active.

PC Bus Style I/O

The PC bus style I/O type of access routes the lower half-word of the ARM bus through the device pro-

viding a direct 16-bit interface. Signals are generated to support the addition of external latches/drivers to

extend the I/O data by 16 bits. The upper half-word of the ARM data bus is routed through these external

devices if present.

There are five different address areas that generate five different chip selects using the same type of

access. There are four fixed-cycle types based on the 16-MHz clock, although the largest area only sup-

ports two of these cycle types. Any access can be held up by external circuitry removing the READY sig-

nal before the end of the cycle.

During these accesses, the relevant chip select is asserted, as well as the appropriate read or write

strobes.

Two special inputs are provided to allow external circuitry to route the full 32 bits through the 16-bit I/O

bus using multiplexing. This allows, for example, the execution of code from a 16-bit PCMCIA card with

suitable external controller. On a read I/O, if this latching signal is used, the data read back onto the ARM

data bus comes from the I/O bus instead of the external extension latches.

3.7 Other Features

The CL-PS7500FE includes four analog comparators used to create four A-to-D converter channels, and

two serial keyboard/mouse ports.

There are eight general-purpose, open-drain I/O lines that can be used as inputs or open drain outputs

and, if required, as interrupt sources.

An interrupt handler processes a variety of internal and external interrupt sources to generate the IRQ

and FIQ interrupts for the ARM processor.

3.8 Test Modes

The CL-PS7500FE has an nTEST pin used to invoke various test modes. When nTEST is set low, the

functionality of many of the pins change depending on the values applied to the nINT3, nINT6 and nINT8

pins. The nTEST pin includes an on-chip pull-up resistor, but it is recommended that the pin be also pulled

up to VDD externally. See Appendix F.

NOTE: The nTEST pin should never be forced low during normal operation.

3.9 Structure of the CL-PS7500FE

The CL-PS7500FE includes three modified ARM macrocells:

q ARM processor

q FPA

q Video and sound macrocells

These macrocells are self-contained and the relevant control registers are contained within them. This

has the effect that there are four sets of programmable registers within the CL-PS7500FE, which are

accessed in different ways depending on their location.

June 1997

ADVANCE DATA BOOK v2.0

31

FUNCTIONAL DESCRIPTION

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