CL-PS7500FE 查看數據表（PDF） - Cirrus Logic
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CL-PS7500FE Datasheet PDF : 251 Pages
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CL-PS7500FE
System-on-a-Chip for Internet Appliance
6.3.5 Section Descriptor
Bit
3:2
(C, B)
4
8:5
11:10
(AP)
19:12
31:20
Description
Control the cache- and write-buffer-related functions as follows:
q C – Cacheable: data at this address is placed in the cache (if the cache is enabled).
q B – Bufferable: data at this address is written through the write buffer (if enabled).
Write as ‘1’ for backward compatibility.
Specify one of the sixteen possible domains (held in the Domain Access Control register) that contain the pri-
mary access controls.
Specify the access permissions for this section (see Table 6-2). The interpretation depends upon the setting of
the S and R bits (control register bits 8 and 9). Note that the Domain Access Control specifies the primary
access control; the AP bits only have an effect in Client mode. Refer to Section 6.9.
Always write as ‘0’.
Form the corresponding bits of the physical address for the 1-Mbyte section.
Table 6-2. Interpreting Access Permission (AP) Bits
AP
S
R
Supervisor
User
Permissions Permissions
Notes
00
0
00
1
00
0
00
1
01
Xa
10
X
11
X
XX
1
0
No access
0
Read only
1
Read only
1
Reserved
X
Read/write
X
Read/write
X
Read/write
1
Reserved
No access
No access
Read only
No access
Read only
Read/write
Any access generates a permission fault.
Supervisor read-only permitted.
Any write generates a permission fault.
Access allowed only in Supervisor mode.
Writes in User mode cause permission fault.
All access types permitted in both modes.
a ‘X’ indicates a don’t care state.
6.4 Translating Section References
Figure 6-6 on page 44 illustrates the complete Section translation sequence. Note that the access per-
missions contained in the Level One descriptor must be checked before the physical address is gener-
ated. The sequence for checking access permissions is described in Section 6.10.4 on page 50.
6.4.1 Level Two Descriptor
If the Level One fetch returns a Page Table descriptor, this provides the base address of the page table
to be used. The page table is then accessed as described in Figure 6-7 on page 45, and a Page Table
42
ARM PROCESSOR MMU
ADVANCE DATA BOOK v2.0
June 1997
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