CL-PS7500FE 查看數據表（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

There is also an interrupt mask and status bit for the sound channel that allows the status of the sound

DMA state machine to be monitored. The state machine generates an interrupt when the end of the cur-

rent buffer is reached, and it is up to the system software to take appropriate action to reprogram that

channel as required while DMA continues from the location pointed to by the other set of buffers.

Sound data is requested by the CL-PS7500FE sound subsystem that asserts a request signal, and the

bus controller arbitrates in favor of the sound DMA when the current bus cycle has completed as long as

there is not an outstanding video or cursor DMA request.

9.3.4 The Sound DMA State Machine

The sound DMA channel is controlled by a simple state machine. The state machine remains in an idle

state when the enable bit in the sound DMA control register has not been set. The state bits of the state

machine are directly mapped to the Sound DMA status register, where they are named Overrun, Int and

A/B. On reset, the state machine is set to ‘110’, setting the Overrun and Int bits. The Overrun bit indicates

when a channel has stopped because it has finished a transfer and the other pointer pair is not pro-

grammed. The Int bit indicates when the channel is requesting an interrupt. The A/B bit indicates the pair

of current/end pointers in use.

The state machine diagram in Figure 9-1 on page 77 shows how the state machine transfers between

buffers A and B to allow DMA to continue uninterrupted when both sets of DMA address registers have

been programmed. The transitions between states occur either when the ARM processor programs an

pointer register pair, or when a buffer is completed. To ensure correct operation, the current pointer must

be programmed before the end pointer as it is the action of programming the end pointer that causes the

state transition. The ‘stop’ bit in the end register terminates a sequence of DMA, by forcing the state

machine back into one of the idle states at the end of the last buffer.

During operation of the state machine, when the end of one buffer is reached, an interrupt is generated

that can be used to signal to the ARM processor that it is time to reprogram that pair of pointers. If one

buffer’s address pointers have not been reprogrammed before the other buffer is exhausted, then both the

Int and Overrun bits are set, and DMA cannot continue until the pointers are reprogrammed.

76

MEMORY SUBSYSTEMS

ADVANCE DATA BOOK v2.0

June 1997

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