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CL-PS7500FE 查看數據表(PDF) - Cirrus Logic

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CL-PS7500FE Datasheet PDF : 251 Pages
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CL-PS7500FE
System-on-a-Chip for Internet Appliance
10. MEMORY AND I/O PROGRAMMERS’ MODEL
10.1 Introduction
The CL-PS7500FE contains over 100 programmable registers (in addition to those in the ARM processor
and the 256 video palette entries), grouped into three sets. Registers inside the ARM processor are
described in Those inside the video and sound macrocell are all programmed by writing to memory loca-
tions 0x03400000 to 0x034FFFFF, with the upper bits of the programmed data determining which
video/sound register is to be programmed. All these registers are write-only, and are described in
Chapter 12 and Chapter 13. The remaining CL-PS7500FE registers are programmed by writing a full 32-
bit data word to an address between 0x03200000 and 0x032001F8. Although most of these registers are
only 8- or 16-bits wide, all the register addresses are word-aligned. All the CL-PS7500FE registers that
do not form part of the ARM processor or the video and sound macrocell are described in the following
sections.
10.2 Register Summary
In Table 10-1, all addresses are hex and relative to the base address 0x03200000.
Table 10-1. CL-PS7500FE Registers
Name
IOCR
KBDDAT
KBDCR
IOLINES
IRQSTA
IRQRQA
IRQMSKA
SUSMODE
IRQSTB
IRQRQB
IRQNSKB
STOPMODE
FIQST
FIQRQ
FIQMSK
CLKCTL
T0low
Address
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C
40
Size
(Bits)
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Read
a










#





Write
Function




#b


SUSPEND
#
#

STOP
#
#



I/O control
Keyboard data
Keyboard control
General-purpose I/O lines
IRQA status
IRQA request/clear
IRQA mask
Enter SUSPEND mode
IRQB status
IRQB request
IRQB mask
Enter STOP mode
FIQ status
FIQ request
FIQ mask
Clock divider control
Timer 0 low bits
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78
MEMORY AND I/O PROGRAMMERS’ MODEL
ADVANCE DATA BOOK v2.0
June 1997

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