Z8018220ASC 查看數據表（PDF） - Zilog

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Z8018220ASC

ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

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Zilog

PRELIMINARY

Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

Z85230 ESCC™ CONTROL REGISTERS

See Figures 52 and 53 for the ESCC Control registers. For

additional information, refer to the ESCC Product

Specification /Technical Manual.

The Z80182/Z8L182 has two ESCC channels. They can be

accessed in any page of I/O space since only the lowest

eight address lines are decoded for access. Their Z180™

MPU Address locations are shown in Table 11.

When the 16550 MIMIC interface is enabled, ESCC channel

B is disconnected from the output pins. The channel B

/TRxCB clock is connected to the Transmit and Receive

timers of the 16550 MIMIC interface. It is recommended

that /TRxCB be programmed as an output with proper

baud rate values to timeout the transmitter and receiver

of the 16550 MIMIC interface.

ESCC Channel A

ESCC Channel B

Table 11. ESCC Control and Data Map

Control

Data

Z180 MPU Address xxE0H

Z180 MPU Address xxE1H

Control

Data

Z180 MPU Address xxE2H

Z180 MPU Address xxE3H

DS971820600

PS009801-0301

3-49

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