FDC37B78X 查看數據表（PDF） - SMSC -> Microchip

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FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

Internal PWRGOOD

An internal PWRGOOD logical control is

included to minimize the effects of pin-state

uncertainty in the host interface as Vcc cycles on

and off. When the internal PWRGOOD signal is

“1” (active), Vcc is > 4V, and the FDC37B78x

host interface is active. When the internal

PWRGOOD signal is “0” (inactive), Vcc is ≤ 4V,

and the FDC37B78x host interface is inactive;

that is, ISA bus reads and writes will not be

decoded.

The FDC37B78x device pins nPME, KCLK,

MCLK, IRRX, nRI1, nRI2, RXD1, RXD2, nRING,

Button_In and GP53 are part of the PME

interface and remain active when the internal

PWRGOOD signal has gone inactive, provided

VTR is powered. In addition, the nPowerOn and

CLK32OUT pins remain active when the internal

PWRGOOD is inactive and VTR is powered.

When the internal PWRGOOD is inactive, and

VTR is powered, the GPIOs (excluding GP53)

become tri-state (input) and are able to generate

wake-up events. The internal PWRGOOD

signal is also used to determine the clock

source for the CIrCC CIR and to disable the IR

Half Duplex Timeout.

Note: If VTR is to be used for programmable

wake-up events when VCC is removed, VTR must

be at its full minimum potential at least 10 µs

before Vcc begins a power-on cycle. When VTR

and Vcc are fully powered, the potential

difference between the two supplies must not

exceed 500mV.

CIRCC PLL Power Control

The FDC37B78x uses the 32.768 kHz RTC

clock and a clock multiplier (PLL) to drive the

CIrCC Wakeup function when Vcc has been

removed. The CIR PLL Power bit, located in the

Sleep/Wake Configuration Register, is used to

enable (power-up) the 32.768 kHz clock PLL.

When the CIR PLL Power bit is set to “1”

(active), the 32.768 kHz clock PLL is running

and can replace the 14.318 MHz clock source

for the CIR Wake Event, depending upon the

state of the internal PWRGOOD signal (TABLE

51). When the CIR PLL Power bit is reset to “0”

(inactive/default), the 32.768 kHz clock PLL is

unpowered.

PLL CONTROL

BIT (CR24.1)

1

0

0

0

0

TABLE 51 - FDC37B78x PLL CONTROLS AND SELECTS

CIR PLL

INTERNAL

POWER BIT PWRGOOD

DESCRIPTION

X

X

All PLLs Powered Down

0

0

0

1

32KHz PLL Unpowered, Not Selected,

14MHz PLL Powered, Selected.

1

0

32KHz PLL Powered, Selected,

14MHz PLL Unpowered, Not Selected.

1

1

32KHz PLL Powered, Not Selected, 14MHz PLL

Powered, Selected.

32.768 kHz Standby Clock Output

The FDC37B78x provides a 32.768 kHz trickle clock output pin. This output is active as long as VTR is

present.

116

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