FDC37B78X 查看數據表（PDF） - SMSC -> Microchip

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FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

therefore only the Host controller can initiate

the first Start Frame. Slaves must

continuously sample the Stop Frames pulse

width to determine the next IRQSER Cycle’s

mode.

IRQSER Data Frame

Once a Start Frame has been initiated, the

FDC37B78x will watch for the rising edge of the

Start Pulse and start counting IRQ/Data Frames

from there. Each IRQ/Data Frame is three

clocks: Sample phase, Recovery phase, and

Turn-around phase. During the Sample phase

the FDC37B78x must drive the IRQSER (SIRQ

pin) low, if and only if, its last detected IRQ/Data

value was low. If its detected IRQ/Data value is

high, IRQSER must be left tri-stated. During the

Recovery phase the FDC37B78x must drive the

SERIRQ high, if and only if, it had driven the

IRQSER low during the previous Sample Phase.

During the Turn-around Phase the FDC37B78x

must tri-state the SERIRQ. The FDC37B78x will

drive the IRQSER line low at the appropriate

sample point if its associated IRQ/Data line is

low, regardless of which device initiated the

Start Frame.

The Sample Phase for each IRQ/Data follows

the low to high transition of the Start Frame

pulse by a number of clocks equal to the

IRQ/Data Frame times three, minus one. (e.g.

The IRQ5 Sample clock is the sixth IRQ/Data

Frame, (6 x 3) - 1 = 17th clock after the rising

edge of the Start Pulse).

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