RUN STATE GPIO DATA REGISTER ACCESS
The GPIO data registers as well as the
Watchdog Timer Control, and the Soft Power
Enable and Status registers can be accessed by
the host when the chip is in the run state if
CR03 Bit[7] = 1. The host uses an Index and
Data port to access these registers. The Index
and Data port power-on default addresses are
0xEA and 0xEB respectively. In the
configuration state the Index port address may
be re-programmed to 0xE0, 0xE2, 0xE4 or
0xEA; the Data port address is automatically set
to the Index port address + 1. Upon exiting the
configuration state the new Index
and Data port addresses are used to access the
GPIO data, Soft Power Status and Enable, and
the Watchdog Timer Control registers.
For example, to access the GP1 data register
when in the run state, the host should perform
an I/O Write of 0x01 to the Index port address
(0xEX) to select GP1 and then read or write the
Data port (at Index+1) to access the GP1
register. Generally, to access any GPIO data
register GPx the host should perform an I/O
Write of 0x0X to the Index port address and then
access GPX through the Data port. The Soft
Power and Watchdog Timer Control registers
are accessed similarly.
PORT
NAME
Index
Data
TABLE 53 - INDEX AND DATA PORTS
PORT
ADDRESS
RUN STATE ACCESS
0xE0, E2, E4, EA 0x01-0x0F
Index address + 1
Access to GP1, Watchdog Timer Control,
GP5, GP6, and the Soft Power Status and
Enable registers (see TABLE 54).
TABLE 54 - RUN STATE ACCESSABLE CONFIGURATION REGISTERS
RUN STATE REGISTER
ADDRESS (INDEX)
REGISTER (CONFIGURATION STATE ADDRESSING1)
0x01
GP1 (L8 - CRF6)
0x03
Watchdog Timer Control (L8 - CRF4)
0x05
GP5 (L8 - CRF9)
0x06
GP6 (L8 - CRFA)
0x08
Soft Power Enable Register 1 (L8-CRB0)
0x09
Soft Power Enable Register 2 (L8-CRB1)
0x0A
Soft Power Status Register 1 (L8-CRB2)
0x0B
Soft Power Status Register 2 (L8-CRB3)
Note 1: These registers can also be accessed through the configuration registers L8 - CRxx, as
shown, when the FDC37B78x is in the configuration state.
124