FDC37B78X 查看數據表（PDF） - SMSC -> Microchip

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FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

KEYBOARD ISA INTERFACE

The FDC37B78x ISA interface is functionally

compatible with the 8042-style host interface. It

consists of the D0-7 data bus; the nIOR, nIOW

and the Status register, Input Data register, and

Output Data register. TABLE 57 shows how the

interface decodes the control signals. In

addition to the above signals, the host interface

includes keyboard and mouse IRQs.

TABLE 57 - ISA I/O ADDRESS MAP

ISA ADDRESS nIOW

nIOR

BLOCK

FUNCTION (NOTE 1)

0x60

0

1

KDATA Keyboard Data Write (C/D=0)

1

0

KDATA Keyboard Data Read

0x64

0

1

KDCTL Keyboard Command Write (C/D=1)

1

0

KDCTL Keyboard Status Read

Note 1:These registers consist of three separate 8 bit registers. Status, Data/Command Write and

Data Read.

Keyboard Data Write

Keyboard Command Write

This is an 8 bit write only register. When

written, the C/D status bit of the status register

is cleared to zero and the IBF bit is set.

This is an 8 bit write only register. When

written, the C/D status bit of the status register

is set to one and the IBF bit is set.

Keyboard Data Read

Keyboard Status Read

This is an 8 bit read only register. If enabled by

"ENABLE FLAGS", when read, the KIRQ output

is cleared and the OBF flag in the status register

is cleared. If not enabled, the KIRQ and/or

AUXOBF1 must be cleared in software.

This is an 8 bit read only register. Refer to the

description of the Status Register for more

information.

CPU-to-Host Communication

The FDC37B78x CPU can write to the Output

Data register via register DBB. A write to

this register automatically sets Bit 0 (OBF) in

the Status register. See Table 58.

8042 INSTRUCTION

OUT DBB

Table 58 - Host Interface Flags

FLAG

Set OBF, and, if enabled, the KIRQ output signal goes high

130

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