FDC37B78X 查看數據表（PDF） - SMSC -> Microchip

零件编号

产品描述 (功能)

生产厂家

FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

8042

P21

0

0

1

1

nGATEA20

ALT_A20

0

1

0

1

System

nA20M

0

1

1

1

Bit 0 of Port 92, which generates the nALT_RST

signal, is used to reset the CPU under program

control. This signal is AND’ed together

externally with the reset signal (nKBDRST) from

the keyboard controller to provide a software

means of resetting the CPU. This provides a

faster means of reset than is provided by the

keyboard controller. Writing a 1 to bit 0 in the

Port 92 Register causes this signal to pulse low

for a minimum of 6µs, after a delay of a

minimum of 14µs.

Before another nALT_RST pulse can be

generated, bit 0 must be set to 0 either by a

system reset of a write to Port 92. Upon reset,

this signal is driven inactive high (bit 0 in the

Port 92 Register is set to 0).

If Port 92 is enabled, i.e., bit 2 of KRST_GA20 is

set to 1, then a pulse is generated by writing a 1

to bit 0 of the Port 92 Register and this pulse is

AND’ed with the pulse generated from the 8042.

This pulse is output on pin KRESET and its

polarity is controlled by the GPI/O polarity

configuration.

135

Share Link: