FDC37B78X 查看數據表（PDF） - SMSC -> Microchip

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FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

When RESET_DRV is active and the battery

voltage is below 1-volt nominal, the following

occurs:

1. Registers 00-0D are initialized to 00h.

2. Access to all registers from the host are

blocked.

RTC Interrupt

RESET_DRV or reading register C clears the

RTC interrupt.

The RTC Interrupt is brought out by

programming the RTC Primary Interrupt Select

to a non-zero value. If IRQ 8 is selected then

the polarity of this IRQ 8 output is

programmable through a bit in the OSC Global

Configuration Register.

The interrupt generated by the RTC is an active

high output. The RTC interrupt output remains

high as long as the status bit causing the

interrupt is present and the corresponding

interrupt-enable bit is set.

Activating

Internal Registers

Table 62 shows the address map for bank 0 of

the RTC; time, calendar, alarm, control, status

bytes and 114 bytes of "CMOS" registers.

ADDRESS

0

1

2

3

4

5

6

7

8

9

A

B

C

D

0E-7Ch

7Dh

7Eh

7Fh

Table 62 - Real Time Clock Address Map, Bank 0

REGISTER TYPE

REGISTER FUNCTION

R/W

Register 0: Seconds

R/W

Register 1: Seconds Alarm

R/W

Register 2: Minutes

R/W

Register 3: Minutes Alarm

R/W

Register 4: Hours

R/W

Register 5: Hours Alarm

R/W

Register 6: Day of Week

R/W

Register 7: Date of Month

R/W

Register 8: Month

R/W

Register 9: Year

R/W

Register A:

R/W

Register B: (Bit 0 is Read Only)

R

Register C:

R/W

Register D:VRT and Day of Month Alarm

R/W

Register E-7C: General Purpose

R/W

Register 7D: Century Byte

R/W

Register 7E: Control Register 1

R/W

Register 7F:General Purpose

All 14 bytes are directly writable and readable by the host with the following exceptions:

a. Register C is read only

b. Bit 7 of Register A and Bit 7 of Register D are read only

c. Bit 0 of Register B is read only

139

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