FDC37B78X 查看數據表（PDF） - SMSC -> Microchip

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FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

General Purpose ACPI Events

The General Purpose ACPI events are enabled

through the SCI_EN1 bit in the GPE_EN

register. This bit, if set, allows any of the

enabled PME events to generate an SCI. In

addition, if the DEVINT_EN bit in the PME_EN 1

Register is set, and if the EN_SMI_PME bit in

the SMI_EN 2 register is set, then any of the

SMI Events can also generate an SCI. See the

SCI/PME and SMI/PME logic diagrams below.

Device Sleep States

Each device in the FDC37B78x supports two

device sleep states, D0 (on) and D3 (off). The

D3 state corresponds to the PCI defined D3cold

state. With all devices off, the part is powered

either by main power (Vcc) or standby power

(Vtr), depending on the system sleep state. In

both cases, the part can provide wakeup

capability through the soft power management

logic and generate a nPME or nSCI. In an ACPI

system, the devices are powered on and off

through control methods.

Wake Events

Wake events are events that turn power on

(activate nPowerOn output) if enabled. These

events can also be enabled as SMI, SCI and

nPME events as shown in the following table. In

addition, these wake events set the WAK_STS

bit if enabled (see ACPI PM1_STS2 Register

description).

INPUT TO SOFT POWER

SMI/SCI/PME

WAKE EVENTS

MANAGEMENT

GENERATION

Pins KCLK

KCLK

SMI/SCI/PME

MCLK

MCLK

SMI/SCI/PME

IRRX2 (Includes CIR)

IRRX2

SMI/SCI/PME

RXD2/IRRX (Includes CIR)

RXD2/IRRX

SMI/SCI/PME

(CIR)

RXD1

CIR

RXD1

SMI/SCI/PME

SMI/SCI1/PME1

nRI1

nRI1

SMI/SCI/PME

nRI2

nRI2

SMI/SCI/PME

Internal

nRING

Button

GP10-17

GP50-54, GP60-67

RTC Alarm (includes AL_REM)

nRING

Button

GPINT1

GPINT2

RTC Alarm + AL_REM

SMI/SCI/PME

SMI/SCI2/PME1

SMI/SCI1/PME

SMI/SCI1/PME1

SCI2

Signals VTR POR

VTR POR

SCI

Note 1: These SCI/PME events are SMI events that are enabled through DEVINT_EN

Note 2: These SCI events have Status and Enable bits in the PM1 registers

The following are SMI events that are not wake events:

• Floppy Interrupt

•

• Parallel Port Interrupt

•

• WDT

•

• P12

UART1 and UART2 interrupts

Mouse and keyboard interrupts

SLP_EN

Any wakeup logic that affects the configuration of the wakeup events is implemented so that the

configuration of the wakeup events is retained (in the event of total power loss) upon Vtr POR.

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